Optimization of Single Flux Quantum Circuit Based Comparators Using Pso

Abstract

In the recent years, a number of groups have shown that 1-bit comparators are suitable candidates for a number of circuits such as front-end of the low temperature detector readout circuits and analog to digital converters. Even though a number of tools exist for the development of digital logic gates, we are not aware of any optimizer for analog circuits that takes into account the stochastic effects in the Josephson junctions. Comparator circuits contain just a few parameters and have been analyzed extensively by a number of groups for over a decade. However, designing the comparator cells by hand is tedious work since it is based on the statistical analysis of the input-output relations of the cell. For the result to be reliable enough, statistically meaningful number of input SFQ pulses should be generated and corresponding output pulses should be analyzed. In addition, the design parameters should be suitable for fabrication and compatible for the rest of the cell library. In this work, we report an optimization tool to find the possible minimum gray-zone width, limited by the process design rules, for single flux quantum circuit based comparators. We used Particle Swarm Optimization (PSO) algorithm to determine the minimum possible gray zone width of a 1-bit comparator. To test the reliability of the PSO algorithm, we made a brute force sweep for a quasi-one-junction SQUID (QOS) with five parameters of the comparator, namely, three junction critical currents, one inductance value, and bias current. We find that the PSO gray zone results closely matches, even exceeds, the brute force design values and takes at least two orders of magnitude less computation time.