Please use this identifier to cite or link to this item: https://hdl.handle.net/20.500.11851/6458
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dc.contributor.authorTang, Xulong-
dc.contributor.authorKandemir, Mahmut Taylan-
dc.contributor.authorKaraköy, Mustafa-
dc.contributor.authorArunachalam, Meenakshi-
dc.date.accessioned2021-09-11T15:36:39Z-
dc.date.available2021-09-11T15:36:39Z-
dc.date.issued2019en_US
dc.identifier.citation40th ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI) part of ACM's Federated Computing Research Conference (FCRC) -- JUN 22-26, 2019 -- Phoenix, AZen_US
dc.identifier.isbn978-1-4503-6712-7-
dc.identifier.urihttps://doi.org/10.1145/3314221.3314599-
dc.identifier.urihttps://hdl.handle.net/20.500.11851/6458-
dc.description.abstractMinimizing cache misses has been the traditional goal in optimizing cache performance using compiler based techniques. However, continuously increasing dataset sizes combined with large numbers of cache banks and memory banks connected using on-chip networks in emerging many-cores/accelerators makes cache hit-miss latency optimization as important as cache miss rate minimization. In this paper, we propose compiler support that optimizes both the latencies of last-level cache (LLC) hits and the latencies of LLC misses. Our approach tries to achieve this goal by improving the parallelism exhibited by LLC hits and LLC misses. More specifically, it tries to maximize both cache-level parallelism (CLP) and memory-level parallelism (MLP). This paper presents different incarnations of our approach, and evaluates them using a set of 12 multithreaded applications. Our results indicate that (i) optimizing MLP first and CLP later brings, on average, 11.31% performance improvement over an approach that already minimizes the number of LLC misses, and (ii) optimizing CLP irst and MLP later brings 9.43% performance improvement. In comparison, balancing MLP and CLP brings 17.32% performance improvement on average.en_US
dc.description.sponsorshipAssoc Comp Machinery, ACM SIGPLANen_US
dc.description.sponsorshipNSFNational Science Foundation (NSF) [1526750, 1763681, 1439057, 1439021, 1629129, 1409095, 1626251, 1629915]; IntelIntel Corporationen_US
dc.description.sponsorshipThe authors thank PLDI reviewers for their constructive feedback, and Jennifer B. Sartor, for shepherding this paper. This research is supported in part by NSF grants #1526750, #1763681, #1439057, #1439021, #1629129, #1409095, #1626251, #1629915, and a grant from Intel.en_US
dc.language.isoenen_US
dc.publisherAssoc Computing Machineryen_US
dc.relation.ispartofProceedings of The 40Th Acm Sigplan Conference On Programming Language Design And Implementation (Pldi '19)en_US
dc.rightsinfo:eu-repo/semantics/openAccessen_US
dc.subjectManycore systemsen_US
dc.subjectdata access parallelismen_US
dc.titleCo-Optimizing Memory-Level Parallelism and Cache-Level Parallelismen_US
dc.typeConference Objecten_US
dc.departmentFaculties, Faculty of Engineering, Department of Computer Engineeringen_US
dc.departmentFakülteler, Mühendislik Fakültesi, Bilgisayar Mühendisliği Bölümütr_TR
dc.identifier.startpage935en_US
dc.identifier.endpage949en_US
dc.identifier.wosWOS:000523190300062en_US
dc.identifier.scopus2-s2.0-85067638402en_US
dc.institutionauthorKaraköy, Mustafa-
dc.identifier.doi10.1145/3314221.3314599-
dc.relation.publicationcategoryKonferans Öğesi - Uluslararası - Kurum Öğretim Elemanıen_US
dc.relation.conference40th ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI) part of ACM's Federated Computing Research Conference (FCRC)en_US
item.openairetypeConference Object-
item.languageiso639-1en-
item.grantfulltextnone-
item.fulltextNo Fulltext-
item.openairecristypehttp://purl.org/coar/resource_type/c_18cf-
item.cerifentitytypePublications-
Appears in Collections:Bilgisayar Mühendisliği Bölümü / Department of Computer Engineering
Scopus İndeksli Yayınlar Koleksiyonu / Scopus Indexed Publications Collection
WoS İndeksli Yayınlar Koleksiyonu / WoS Indexed Publications Collection
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