Analysis of Delay and Jitter of Rapid Single Flux Quantum Wiring Cells

Abstract

Rapid Single Flux Quantum (RSFQ) computing is a developing technology that enables high speed computing such as microprocessors, network routers and analog to digital converters. However, as the complexity and the computing speed of these circuits increase, timing errors of individual gates become more relevant. Most of these timing errors occur on the signal distribution path due to the use of a large number of wiring cells but these effects are mostly ignored. Hence future circuit optimization tools should take both delay and jitter amount into account. Therefore, delay and jitter values of single and cascaded fundamental RSFQ wiring cells, namely Josephson transmission lines (JTL), splitters, and mergers, are analyzed. Also, low bias voltage driving of the circuit and the dependence on input signal frequency effects are observed. In conclusion, jitter and delay values depending on the aforementioned parameters for single gates and cascaded gates are reported.