A 9.95-11.3-Gb/s XFP transceiver in 0.13-mu m CMOS

Abstract

A 9.95-11.3-Gb/s transceiver in 0.13-mu m CMOS for XFP modules is presented. The CDR uses a dual-loop DLL/PLL with a binary phase detector to exceed XFP jitter specifications. The dual loop solves the problem of having a controlled jitter transfer bandwidth with a binary phase detector. A half rate binary phase detector with a 2:1 serializer implements full-rate I/O. Dispersion jitter from 12" of FR4 is equalized resulting in system JGEN under 4 mUI(RMs) and 35 mUI(PP). Power consumption is 800 mw.