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https://hdl.handle.net/20.500.11851/3842
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DC Field | Value | Language |
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dc.contributor.author | Bolat, A. | - |
dc.contributor.author | Cassano, L. | - |
dc.contributor.author | Reviriego, P. | - |
dc.contributor.author | Ergin, Oğuz | - |
dc.contributor.author | Ottavid, M. | - |
dc.date.accessioned | 2020-10-22T16:40:33Z | - |
dc.date.available | 2020-10-22T16:40:33Z | - |
dc.date.issued | 2020-04 | |
dc.identifier.citation | Bolat, A., Cassano, L., Reviriego, P., Ergin, O. and Ottavid, M. (2020, April). A Microprocessor Protection Architecture against Hardware Trojans in Memories. In 2020 15th Design & Technology of Integrated Systems in Nanoscale Era (DTIS) (pp. 1-6). IEEE. | en_US |
dc.identifier.isbn | 978-172815426-8 | |
dc.identifier.uri | https://hdl.handle.net/20.500.11851/3842 | - |
dc.identifier.uri | https://ieeexplore.ieee.org/document/9080961 | - |
dc.description.abstract | Software exploitable Hardware Trojan Horses (HWTs) have been currently inserted in commercial CPUs and, very recently, in memories. Such attacks may allow malicious users to run their own software or to gain unauthorized privileges over the system. Therefore, HWTs are nowadays considered a serious threat both from academy and industry. This paper presents a protection architecture meant to shield the communication between the CPU and the memory in a microprocessor-based system. The architecture aims at detecting the activation on HWTs infesting the instruction and data memories of the system. Our proposal relies on the use of Bloom Filters (BFs) that are included in ad-hoc designed checkers and integrated in the protection architecture. BFs guarantee zero false alarms and a small (and configurable) percentage of undetected alarms. We applied the protection architecture to a case study system based on a RISC-V microprocessor implemented on an FPGA and running a set of software benchmarks. Our proposal demonstrated to be able to detect more than 99% of possible HWTs activations with zero false alarms. We measured a lookup table overhead ranging from 0.68% up to 10.52% and a flip-flop overhead between 0.68% and 0.99%, and with no working frequency reduction. © 2020 IEEE. | en_US |
dc.language.iso | en | en_US |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | en_US |
dc.relation.ispartof | Proceedings - 2020 15th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2020 | en_US |
dc.rights | info:eu-repo/semantics/closedAccess | en_US |
dc.subject | Bloom Filter | en_US |
dc.subject | hardware security | en_US |
dc.subject | Hardware Trojan Horses | en_US |
dc.subject | Microprocessor-based System | en_US |
dc.subject | RISC-V | en_US |
dc.title | A Microprocessor Protection Architecture Against Hardware Trojans in Memories | en_US |
dc.type | Conference Object | en_US |
dc.department | Faculties, Faculty of Engineering, Department of Computer Engineering | en_US |
dc.department | Fakülteler, Mühendislik Fakültesi, Bilgisayar Mühendisliği Bölümü | tr_TR |
dc.authorid | 0000-0003-0784-8365 | - |
dc.identifier.wos | WOS:000588563400005 | en_US |
dc.identifier.scopus | 2-s2.0-85085176704 | en_US |
dc.institutionauthor | Ergin, Oğuz | - |
dc.identifier.doi | 10.1109/DTIS48698.2020.9080961 | - |
dc.relation.publicationcategory | Konferans Öğesi - Uluslararası - Kurum Öğretim Elemanı | en_US |
item.openairetype | Conference Object | - |
item.languageiso639-1 | en | - |
item.grantfulltext | none | - |
item.fulltext | No Fulltext | - |
item.openairecristype | http://purl.org/coar/resource_type/c_18cf | - |
item.cerifentitytype | Publications | - |
crisitem.author.dept | 02.3. Department of Computer Engineering | - |
Appears in Collections: | Bilgisayar Mühendisliği Bölümü / Department of Computer Engineering Scopus İndeksli Yayınlar Koleksiyonu / Scopus Indexed Publications Collection WoS İndeksli Yayınlar Koleksiyonu / WoS Indexed Publications Collection |
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