Please use this identifier to cite or link to this item: https://hdl.handle.net/20.500.11851/1976
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dc.contributor.authorHassan, Hasan-
dc.contributor.authorVijaykumar, Nandita-
dc.contributor.authorKhan, Samira-
dc.contributor.authorGhose, Saugata-
dc.contributor.authorChang, Kevin-
dc.contributor.authorPekhimenko, Gennady-
dc.contributor.authorLee, Donghyuk-
dc.contributor.authorErgin, Oğuz-
dc.contributor.authorMutlu, Onur-
dc.date.accessioned2019-07-10T14:42:43Z
dc.date.available2019-07-10T14:42:43Z
dc.date.issued2017
dc.identifier.citationHassan, H., Vijaykumar, N., Khan, S., Ghose, S., Chang, K., Pekhimenko, G., ... & Mutlu, O. (2017, February). SoftMC: A flexible and practical open-source infrastructure for enabling experimental DRAM studies. In 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA) (pp. 241-252). IEEE.en_US
dc.identifier.isbn978-1-5090-4985-1
dc.identifier.issn1530-0897
dc.identifier.urihttps://ieeexplore.ieee.org/document/7920829-
dc.identifier.urihttps://hdl.handle.net/20.500.11851/1976-
dc.description23rd IEEE International Symposium on High Performance Computer Architecture (HPCA) (2017 : Austin, TX)
dc.description.abstractDRAM is the primary technology used for main memory in modern systems. Unfortunately, as DRAM scales down to smaller technology nodes, it faces key challenges in both data integrity and latency, which strongly affects overall system reliability and performance. To develop reliable and high-performance DRAM-based main memory in future systems, it is critical to characterize, understand, and analyze various aspects (e.g., reliability, latency) of existing DRAM chips. To enable this, there is a strong need for a publicly-available DRAM testing infrastructure that can flexibly and efficiently test DRAM chips in a manner accessible to both software and hardware developers. This paper develops the first such infrastructure, SoftMC (Soft Memory Controller), an FPGA-based testing platform that can control and test memory modules designed for the commonly-used DDR (Double Data Rate) interface. SoftMC has two key properties: (i) it provides flexibility to thoroughly control memory behavior or to implement a wide range of mechanisms using DDR commands; and (ii) it is easy to use as it provides a simple and intuitive high-level programming interface for users, completely hiding the low-level details of the FPGA. We demonstrate the capability, flexibility, and programming ease of SoftMC with two example use cases. First, we implement a test that characterizes the retention time of DRAM cells. Experimental results we obtain using SoftMC are consistent with the findings of prior studies on retention time in modern DRAM, which serves as a validation of our infrastructure. Second, we validate two recently-proposed mechanisms, which rely on accessing recently-refreshed or recently-accessed DRAM cells faster than other DRAM cells. Using our infrastructure, we show that the expected latency reduction effect of these mechanisms is not observable in existing DRAM chips, which demonstrates the usefulness of SoftMC in testing new ideas on existing memory modules. We discuss several other use cases of SoftMC, including the ability to characterize emerging non-volatile memory modules that obey the DDR standard. We hope that our open-source release of SoftMC fills a gap in the space of publicly-available experimental memory testing infrastructures and inspires new studies, ideas, and methodologies in memory system design.en_US
dc.description.sponsorshipGoogle; Intel; Nvidia; Samsung; VMware; NSF [1212962, 1320531, 1409723]; Intel Science and Technology Center for Cloud Computing; Semiconductor Research Corporation
dc.language.isoenen_US
dc.publisherIEEEen_US
dc.rightsinfo:eu-repo/semantics/closedAccessen_US
dc.subjectDynamic random access storageen_US
dc.subjectData storage equipmenten_US
dc.subjectRefresh operationsen_US
dc.titleSoftmc: a Flexible and Practical Open-Source Infrastructure for Enabling Experimental Dram Studiesen_US
dc.typeConference Objecten_US
dc.departmentFaculties, Faculty of Engineering, Department of Computer Engineeringen_US
dc.departmentFakülteler, Mühendislik Fakültesi, Bilgisayar Mühendisliği Bölümütr_TR
dc.identifier.startpage241
dc.identifier.endpage252
dc.authorid0000-0003-2701-3787-
dc.identifier.wosWOS:000403330300021en_US
dc.identifier.scopus2-s2.0-85019640353en_US
dc.institutionauthorErgin, Oğuz-
dc.identifier.doi10.1109/HPCA.2017.62-
dc.authorwosidE-5717-2010-
dc.authorscopusid6603141208-
dc.relation.publicationcategoryKonferans Öğesi - Uluslararası - Kurum Öğretim Elemanıen_US
dc.identifier.scopusquality--
item.openairetypeConference Object-
item.languageiso639-1en-
item.grantfulltextnone-
item.fulltextNo Fulltext-
item.openairecristypehttp://purl.org/coar/resource_type/c_18cf-
item.cerifentitytypePublications-
crisitem.author.dept02.3. Department of Computer Engineering-
Appears in Collections:Bilgisayar Mühendisliği Bölümü / Department of Computer Engineering
Scopus İndeksli Yayınlar Koleksiyonu / Scopus Indexed Publications Collection
WoS İndeksli Yayınlar Koleksiyonu / WoS Indexed Publications Collection
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