EasyDRAM: An FPGA-Based Infrastructure for Fast and Accurate End-to-End Evaluation of Emerging DRAM Techniques

Abstract

DRAM is a critical component of modern computing systems. Recent works propose numerous techniques (that we call DRAM techniques) to enhance DRAM-based computing systems' throughput, reliability, and computing capabilities (e.g., in-DRAM bulk data copy). Evaluating the system-wide benefits of DRAM techniques is challenging as they often require modifications across multiple layers of the computing stack. Prior works propose FPGA-based platforms for rapid end-to-end evaluation of DRAM techniques on real DRAM chips. Unfortunately, existing platforms fall short in two major aspects: (1) they require deep expertise in hardware description languages, limiting accessibility; and (2) they are not designed to accurately model modern computing systems.We introduce EasyDRAM, an FPGA-based framework for rapid and accurate end-to-end evaluation of DRAM techniques on real DRAM chips. EasyDRAM overcomes the main drawbacks of prior FPGA-based platforms with two key ideas. First, EasyDRAM removes the need for hardware description language expertise by enabling developers to implement DRAM techniques using a high-level language (C++). At runtime, EasyDRAM executes the high-level software-defined memory system design in a programmable memory controller. Second, EasyDRAM tackles a fundamental challenge in accurately modeling modern systems: real processors typically operate at significantly higher clock frequencies than DRAM, a disparity that is difficult to replicate on FPGA platforms. EasyDRAM addresses this challenge by decoupling the processor-DRAM interface and advancing the system state using a novel technique we call time scaling, which faithfully captures the timing behavior of the modeled system.We validate EasyDRAM's evaluation accuracy by comparing the memory latency profile of a real CPU-based system and its modeled implementation using EasyDRAM. We demonstrate the ease of use of EasyDRAM by evaluating two DRAM techniques end-to-end in a real FPGA-based system: (1) in-DRAM bulk data copy (i.e., RowClone) and (2) reduced-latency DRAM access that exploits the latency variation across DRAM cells. Implementing these two techniques requires no hardware modifications and only 325 lines of C++ code over EasyDRAM's extensible code base. We compare our results to prior FPGA-based platforms. EasyDRAM yields more accurate results (e.g., by ≈20× for execution time) than the state-of-the-art related platform. We believe and hope that EasyDRAM will enable innovative ideas in memory system design to rapidly come to fruition. To aid future research, we open-source our EasyDRAM implementation at https://github.com/CMU-SAFARI/EasyDRAM. © 2025 IEEE.